CPU, Memory and NoC Architectures

Repositories

• CAP Benchmarks: https://github.com/cart-pucminas/CAPBenchmarks

• Tomasulo's Algorithm Simulator: https://github.com/cart-pucminas/tomasulo

• Learning with the Amnesia Simulator: https://github.com/cart-pucminas/amnesia

Publications

1. VIEIRA, J. V.; SOUZA, M. A.; FREITAS, H. C.. Performance Evaluation of Intel and AMD Memory Hierarchies Using a Simulation-driven Approach With Gem5, in Workshop de Iniciação Científica em Arquitetura de Computadores e Computação de Alto Desempenho (WSCAD-WIC), 2023.

2. ROCHA, C.; SANTOS, A. L.; SOUZA, M. A.. A Systematic Literature Review on Optimization Techniques for Quantum Computing Compilers, in Workshop de Iniciação Científica em Arquitetura de Computadores e Computação de Alto Desempenho (WSCAD-WIC), 2023.

3. NOLASCO, T.; VIEIRA, D.; SILVA, J. A. S.; FREITAS, H. C.. Simulador do Algoritmo de Tomasulo com Conjunto de Instruções RISC-V, in Workshop de Iniciação Científica em Arquitetura de Computadores e Computação de Alto Desempenho (WSCAD-WIC), 2023.

4. RIGOTTO, P.; FREITAS, H. C.. Abordagem para Aprendizado do Simulador gem5 para Pesquisadores Iniciantes, in Workshop de Iniciação Científica em Arquitetura de Computadores e Computação de Alto Desempenho (WSCAD-WIC), 2023.

5. VIEIRA D.; NOLASCO, T.; SILVA, J. A. S.; BOUCHARDET, C.; FREITAS, H. C.. Aprendendo Hierarquia de Memória e a Exploração das Localidades Espacial e Temporal com o Simulador Amnesia, in International Journal of Computer Architecture Education (IJCAE), 2023.

6. SOUZA, MATHEUS ; FREITAS, HENRIQUE COTA ; PÉTROT, FRÉDÉRIC . Coherence State Awareness in Way-Replacement Algorithms for Multicore Processors. In: XX Simpósio em Sistemas Computacionais de Alto Desempenho, Campo Grande. 2019. p. 240-251.

7. AMORIM, A. M. P. ; FREITAS, H. C. . Assessing Parallel Thread Mapping Approaches on Shared Memory SMT Architectures. IEEE Latin America Transactions, v. 17, p. 270-279, 2019.

8. SOUZA, MATHEUS A. ; FREITAS, HENRIQUE C. ; MEHAUT, JEAN-FRANCOIS . Design Space Exploration of Energy Efficient NoC-and Cache-Based Many-Core Architecture. 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2018. p. 402-409.

9. SOUZA, M. A. ; PENNA, P. H. M. M. ; QUEIROZ, M. M. ; PEREIRA, A. D. ; GOES, L. F. W. ; FREITAS, H. C. ; CASTRO, M. ; NAVAUX, P. O. A. ; MEHAUT, J-F . CAP Bench: A Benchmark Suite for Performance and Energy Evaluation of Low-Power Many-Core Processors. Concurrency and Computation,  v. 29, Issue 4, p. e3892, February 2017.

10. SOUZA, MATHEUS A. ; COTA, TULIO T. ; QUEIROZ, MATHEUS M. ; FREITAS, HENRIQUE C. . Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading. Workshop on Applications for Multi-Core Architectures (WAMCA). International Symposium on Computer Architecture and High Performance Computing Workshops (SBACPADW), Campinas, 2017. p. 1-6.

11. CARMO, D. A. S. ; SOUZA, M. A. ; FREITAS, H. C. . Avaliação de Topologias de Redes-em-Chip usando Simulação de Sistemas Completos e Aplicações Paralelas. In: Simpósio em Sistemas Computacionais de Alto Desempenho (WSCAD), Aracaju. 2016. p. 276-287.

12. NOVAIS, J. P. P. ; SOUZA, M. A. ; FREITAS, H. C. . Projeto em VHDL de um Processador de Rede Intra-Chip. In: Workshop de Iniciação Científica, 2016, Aracaju. XVII Simpósio em Sistemas Computacionais de Alto Desempenho, 2016. p. 19-24.

13. AMORIM, A. M. P. ; OLIVEIRA, P. A. C. ; FREITAS, H. C. . Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks. Journal of The Brazilian Computer Society (doi), 21:6, 27 June 2015.

14. GARCIA, G. A. G. ; FREITAS, H. C. . Avaliação de Desempenho de um Cluster Raspberry Pi com NAS Parallel Benchmarks. In: Workshop de Iniciação Científica (WIC) - Simpósio em Sistemas Computacionais de Alto Desempenho, Florianópolis, 2015. p. 57-62.

15. AVELAR, C. P. ; PENNA, P. H. M. M. ; FREITAS, H. C. . Algoritmo K-means para Mapeamento Estático de Processos em Redes-em-Chip. In: Simpósio em Sistemas Computacionais de Alto Desempenho (WSCAD), 2014, São José dos Campos. p. 204-215. 2014.

16. SOUZA, M. A.; ALVES, M. A. Z.; FREITAS, H. C.; NAVAUX, P. O. A.. Avaliação do Consumo Energético em Arquiteturas Multi-Core com Memória Cache Compartilhada. In: Workshop em Desempenho de Sistemas Computacionais e de Comunicação (WPerformance), CSBC 2014, Brasília, SBC, p. 1812-1824. 2014.

17. PENNA, P. H. M. M. ; FREITAS, H. C. . Análise e Avaliação de Simuladores de Sistemas Completos para o Ensino de Arquitetura de Computadores. International Journal of Computer Architecture Education, vol. 2, no 1, p.13-16, 2013.

18. [doi] AMORIM, A. M. P. ; FREITAS, H. C. . Avaliação de Desempenho de Redes-em-Chip Sem Fio Single-Hop com NAS Parallel Benchmarks. In: Simpósio em Sistemas Computacionais (WSCAD), Porto de Galinhas. p. 92-99. 2013.

19. ALVES, M. A. Z. ; FREITAS, H. C. ; NAVAUX, P. O. A. . High Latency and Contention on Shared L2-Cache for Many-Core Architectures. Parallel Processing Letters (doi), v. 21, p. 85-106, 2011.

20. RUTZIG, M. B. ; BECK, A. C. S. ; MADRUGA, F. ; ALVES, M. A. ; FREITAS, H. C. ; MAILLARD, N. ; NAVAUX, P. O. A. ; CARRO, L. . Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment. International Journal of Reconfigurable Computing, v. 2011, p. 1-13, 2011.

21. AVELAR, C. P. ; OLIVEIRA, P. A. C. ; FREITAS, H. C. ; NAVAUX, P. O. A. . Evaluating the Problem of Process Mapping on Network-on-chip for Parallel Applications. In: Workshop on Architecture and Multi-Core Applications, Los Alamitos : IEEE Computer Society, Vitória, p. 18-23. 2011.

22. OLIVEIRA, P. A. C. ; DUARTE-FIGUEIREDO, F. L. P. ; MARTINS, C. A. P. S. ; FREITAS, H. C. ; RIBEIRO, C. P. ; CASTRO, M. ; MARANGOZOVA-MARTIN, V. ; MEHAUT, J-F . Performance Evaluation of WiNoCs for Parallel Workloads based on Collective Communications. In: IADIS Applied Computing, p. 307-314, 2011. (Best Paper Award)

23. MADRUGA, F. L. ; FREITAS, H. C. ; NAVAUX, P. O. A. . Parallel Shared-Memory Workloads Performance on Asymmetric Multi-core Architectures, 18th Euromicro International Conference on Parallel, Distributed and Network-Based Computing, PDP. Los Alamitos : IEEE Computer Society, Pisa, p. 163-169. 2010.

24. FREITAS, H. C. ; ALVES, M. A. Z. ; SCHNORR, L. M. ; NAVAUX, P. O. A. . Impact of Parallel Workloads on NoC Architecture Design, 18th Euromicro International Conference on Parallel, Distributed and Network-Based Computing, PDP. Los Alamitos : IEEE Computer Society, Pisa, p. 551-555. 2010.

25. RUTZIG, M. B. ; MADRUGA, F. L. ; ALVES, M. A. Z. ; COTA, H. ; BECK, A. C. S. ; MAILLARD, N. ; NAVAUX, P. O. A. ; CARRO, L. . TLP and ILP exploitation through a Reconfigurable Multiprocessor System, Reconfigurable Architectures Workshop, RAW, in conjunction with IPDPS 2010, Atlanta, p. 1-8. 2010.

26. FREITAS, H. C. ; MADRUGA, F. L. ; ALVES, M. A. Z. ; NAVAUX, P. O. A. . Design of Interleaved Multithreading for Network Processors on Chip, IEEE International Symposium on Circuits and Systems, ISCAS, Taipei, 2009, p. 2213-2216.

27. ALVES, M. A. Z. ; FREITAS, H. C. ; NAVAUX, P. O. A. . Investigation of Shared L2 Cache on Many-Core Processors, International Conference on Architecture of Computing Systems (ARCS). Berlin : VDE VERLAG GMBH, Delft, p. 21-30. 2009.

28. FREITAS, H. C. ; NAVAUX, P. O. A. . On the Design of Reconfigurable Crossbar Switch for Adaptable On-Chip Topologies in Programmable NoC Routers, ACM Great Lakes Symposium on VLSI, GLSVLSI. New York : ACM, Boston, p. 129-132. 2009.

29. FREITAS, H. C.; ALVES, M. A. Z. ; SCHNORR, L. M. ; NAVAUX, P. O. A. . Performance Evaluation of NoC Architectures for Parallel Workloads. In: ACM/IEEE International Symposium on Networks-on-Chip (NOCS), San Diego. 2009. p. 87-87. 

30. FREITAS, H. C. ; SANTOS, T. G. S. ; NAVAUX, P. O. A. . Design of programmable NoC router architecture on FPGA for multi-cluster NoCs. IET/IEEE Electronics Letters (doi), v. 44, p. 969, 2008.

31. FREITAS, H. C. ; NAVAUX, P. O. A. . Evaluating On-Chip Interconnection Architectures for Parallel Processing. IEEE International Symposium on Scientific and Engineering Computing, SEC 2008, in conjunction with CSE 2008. Los Alamitos : IEEE Computer Society Press, São Paulo, p. 188-193. 2008.

32. FREITAS, H. C. ; NAVAUX, P. O. A. . A High-Throughput Multi-Cluster NoC Architecture, IEEE International Conference on Computational Science and Engineering, CSE 2008. Los Alamitos : IEEE Computer Society Press, São Paulo, p. 56-63. 2008.

33. FREITAS, H. C. ; SANTOS, T. G. S. ; NAVAUX, P. O. A. . NoC Architecture Design for Multi-Cluster Chips, IEEE International Conference on Field Programmable Logic and Applications, FPL,  Heidelberg, p. 53-58. 2008.

34. FREITAS, H. C., COLOMBO, D. M., KASTENSMIDT, F. L., NAVAUX, P. O. A., Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs. In: IEEE International Symposium on Circuits and Systems, ISCAS, New Orleans, USA, May 27 – 30, 2007.

35. FREITAS, H. C., RAMOS, L. E. S., CARVALHO, M. B., AMARAL, A. M., DINIZ, A. R. M., MARTINS, C. A. P. S., Reconfigurable Crossbar Switch Architecture for Network Processors. In: IEEE International Symposium on Circuits and Systems, Island of Kos, Greece, pp.4042-4045, May 21 – 24, 2006.

36. FREITAS, H. C.; WAGNER, F. R. ; NAVAUX, P. O. A. ; MARTINS, C. A. P. S. . Projeto de um Processador de Rede Intra-Chip para Controle de Comunicação entre Múltiplos Cores. In: Workshop em Sistemas Computacionais de Alto Desempenho (WSCAD) Ouro Preto. 2006. p. 3-10. (Best Paper Award)